1. Field of the Invention
The present invention relates to a data processing system equipped with a DMA processing unit to transfer data from an external data communication unit to a memory unit.
2. Description of the Prior Art
FIG. 14 is a block diagram showing an arrangement of a data processing unit equipped with a conventional direct memory access processing unit (which will be referred hereinafter to as a DMA processing unit). In FIG. 14, numeral 1 represents a CPU, and 2, 3 designate respectively the components of the CPU 1. The component 2 is a bus interface means (BIU) for performing the fetch of an instruction word and the input/output of data with respect to the CPU 1, and the component 3 is an instruction register (IR) for storing an instruction word to be effected. Further, numeral 4 represents a DMA processing unit, and 5, 6, 7, 8, 9, 10 respectively designate the components of the DMA processing unit 4. The component 5 is a control register (CR) for determining an operation of the DMA processing unit 4; the component 6 is a transferring-source address register (SA) showing an address of the transferring source of data to be transferred by the DMA processing unit 4; the component 7 is a transferring-destination address register (DA) showing an address of a transferring destination of data to be transferred by the DMA processing unit 4; the component 8 is a transfer count register (TC) showing the number of times of the transfer to be effected by the DMA processing unit 4; the component 9 is a control unit of the DMA processing unit 4; and the component 10 is a data register (DR) for temporarily storing the data read out from the transferring source. Moreover, numerals 11, 12, 13 denote an address bus, a data bus and a control signal bus, respectively, and numeral 14 depicts an external data communication unit and 15 indicates a memory unit. The external data communication means 14 and the memory unit 15 are coupled through the address bus 11, the data bus 12 and the control signal bus 13 to the CPU 1 and the DMA processing unit 4.
FIG. 15 shows the contents of the control register 5 of the DMA processing unit 4. In FIG. 15, numeral 16 is a bit indicative of the transfer unit in the DMA transfer where "0" indicates that the transfer unit is byte and "1" indicates that the transfer unit is word. Further, numeral 17 is a bit indicative of the mode of the DMA transfer where "0" indicates the cycle steal mode and "1" indicates the burst mode. Here, the cycle steal mode is an operational mode for DMA transfers to one unit of transfer in response to a DMA transfer request before returning to the CPU 1, and the burst mode is an operational mode for continuous transfers invoked by a DMA transfer request without returning to the CPU 1. Moreover, 18a and 18b are indicative of methods of correcting the address of the transfer source after the DMA transfer is effected in one transfer unit where, when "00", the address of the transfer source is fixed as it is after the DMA transfer, when "01", the address of the transfer source is incremented, when "10", the address of the transfer source is decremented, and "11" is in an unused state. Further, 19a and 19b show the correcting methods of the address of the transfer destination. When "00", the address of the transfer destination is fixed as it is after the DMA transfer, when "01", the address of the transfer destination is incremented, when "10", the address of the transfer destination is decremented, and "11" is in an unused state. Numeral 20 represents a DMA transfer effective flag where "0" indicates that the DMA processing unit is not used and "1" indicates that it is used.
The above-described system is for receiving data from an external device through the external data communication unit 14 and for processing the data in accordance with a procedure stored in the memory unit 15. In this case, when the data communication speed is slower as compared with the processing speed of the CPU 1, this processing procedure is realized by an interruption process. That is, in response to the reception of the data from the external, the external data communication unit 14 requests the CPU 1 to perform an interruption process. In response to this request, the CPU 1 interrupts the currently executing process and saves the program status word and the program counter in a stack and then branches to a program for the above-mentioned processing procedure. In this program there are written instructions for saving general-use registers of the CPU 1, reading the received data from the external data communication unit 14, writing the read data in the memory unit 15, for example. The above-mentioned processing procedure can be effected with this program being executed by the CPU 1.
However, when the communication speed is high, there is the possibility that the next data is supplied before reading the received data from the external data communication means 14, and hence the processing procedure due to the interruption can provide an inconvenience. In this case, a processing procedure using the DMA processing unit 4 is required to be effected. Thus, the interruption request signal of the external data communication unit 14 is arranged to become a DMA transfer request signal with respect to the DMA processing unit 4. Further, since the initialization of the respective registers is required before use, before performing the above-mentioned procedure, the DMA processing unit 4 writes, through the CPU, the control code "10010000" in the control register 5, the read address of the received data of the external data communication means 14 in the transfer-source address register 6, an adequate address of the memory means 15 in the transfer-destination address register 7, and the number of bytes of the coming data in the transfer count register 8.
In response to the reception of the data, the external data communication unit 14 generates an interruption request signal. This signal is inputted as the DMA transfer request signal to the DMA processing unit 4. In response to the input, the DMA processing unit 4 supplies a hold request signal to the CPU 1 which in turn interrupts the currently executing process and opens the address bus 11, the data bus 12 and the control signal bus 13 and further supplies a hold acknowledge signal to the DMA processing signal 4. Thus, the DMA processing unit 4 supplies a DMA acknowledge signal to the external data communication unit 14 so that the received signal is read out from the external data communication unit 14 in accordance with the address stored in the transfer-source address register 6 and temporarily stored in the data register 10. Secondly, this data is written in the memory unit 15 in accordance with the address stored in the transfer-destination address register 7. At the same time, the content of the transfer-destination address register 7 is incremented and the content of the transfer count register 8 is decremented. In response to the completion of the DMA transfer in one unit, the DMA processing unit 4 withdraws the hold request signal, and hence the CPU restarts the interrupted process.
Since a data processing system equipped with the conventional DMA processing unit is thus arranged, the data transfer can be effected even if the processing procedure due to the interruption of the CPU is inconvenient. There is a problem which arises with the system, however, in that the processing content of the DMA processing unit is determined and limited by the control register and hence difficulty is encountered, for example, to meet the requirement that a portion of the process is changed in accordance with the purpose.